In a conventional semiconductor device, trenches are widely used as capacitors for DRAM cells, in which a gate electrode of a MOS transistor is used as a word line, and one of source and drain regions of the MOS transistor is connected to a bit line, while the remaining one of the source and drain regions is used as one of electrodes for the capacitor. In such a capacitor, an insulation film which is grown on an inner wall thereof is a capacitive insulation film, and a conductor which is buried in the interior thereof is a plate electrode.
On the other hand, a substrate is used as a plate electrode (cell plate) in a substrate-plate trench-capacitor (SPT) for avoiding soft error due to .alpha. particles. In this structure, an n well is grown on the surface a p.sup.+ silicon substrate for the plate electrode, and source and drain regions are provided on the n well surface to be in self-alignment relative to a gate electrode for a word line. The SPT capacitor is provided to be proximate to one of the source and drain regions and across the n well surface and the p.sup.+ silicon substrate, and is connected to the proximate region of the source and drain regions by a conduction film grown on the n well surface. The other one of the source and drain regions is connected through a bit contact to a bit line.
For the purpose of providing an improved SPT capacitor, a structure of a merged isolation and node trench (MINT) has been proposed on pages 25 and 26 of "1988 symposium on VLSI technology digest of technical papers".
Although this structure will be explained later in detail, a trench capacitor which is grown at a node of a memory cell functions as a device separation region, so that the size of the memory cell can be small.
However, the conventional semiconductor device of the MINT structure has first to third disadvantages as set out below.
First, a memory cell is limited to be made small in size, because a MOS transistor which is formed on the surface of an n well grown on a p.sup.+ substrate and a storage electrode which is formed in the trench capacitor are connected by a surface strap, so that a predetermined margin of an alignment is required therebetween.
Second, the effect of a parasitic field effect transistor is relieved by the existence of an oxide collar provided at the inner top of the trench capacitor, but it is not sufficient. This is because the oxide collar does not reach the p.sup.+ silicon substrate, so that the storage electrode is in contact only through a capacitive insulation film with the n well. For this structure, the effect of the parasitic field effect transistor is not suppressed, so that leakage occurs between a portion of the source and drain regions and the p.sup.+ silicon substrate.
Third, leakage occurs between the n well and the p.sup.+ silicon substrate due to the formation of a parasitic gate control diode (GCD) formed by the storage electrode, the source and drain regions connected thereto, and the oxide collar.